Programmable ASICs enable stateful network functions at line rate, including emerging in-network inference tasks. However, limited on-chip SRAM constrains the number of flows whose state can be retained, creating a fundamental tension between scalability and inference accuracy. While throughput is rarely the bottleneck, flow concurrency and arrival dynamics directly impact state availability and eviction behavior. Despite this, the behavior of stateful inference under realistic traffic patterns remains poorly understood, in part due to the lack of methodologies for deriving labeled workloads from real traffic traces. In this talk, I will introduce the main challenges behind this problem and our preliminary ideas and ongoing efforts.

About David de Andrés

David is a doctoral candidate at the IMDEA Networks Institute and Universidad Carlos III de Madrid (UC3M). He holds a B.Eng. in Telecommunications from the Universidad Politécnica de Madrid (UPM), and an M.Sc. in Electrical Engineering and Information Technology from the Technical University of Munich (TUM). In addition to his academic work, he has gained professional experience as a software developer at Cognizant Technology Solutions and as a network engineer at Juniper Networks. His research focuses on bringing network intelligence solutions to the user plane using programmable network elements and hardware-aware designs.

This event will be conducted in English