Improving the energy-efficiency of core routers is important for ISPs and equipment vendors alike. We tackle this problem by focusing on packet buffers in backbone router line-cards. We broadly classify the talk into two parts – an evolutionary approach and a clean-slate design. In the former, we propose a simple power saving mechanism that turns buffers on/off to save energy.

Our scheme can be incrementally deployed today and requires minimal changes to existing line-card design. In the latter, we examine the impact of very small buffers when both real-time and TCP traffic coexist in the network.

Then, we envision a near-zero buffer core network and develop a novel edge-to-edge based packet-level forward error correction mechanism to recover the lost packets in the core. We believe that enabling core networks with near-zero buffers can pave the way for single-chip line-cards, which can not only increase router capacity significantly but also offer dramatic energy savings in the years to come.

Who is Dr. Arun Vishwanath?

Arun Vishwanath completed his PhD in the School of Electrical Engineering and Telecommunications, University of New South Wales (UNSW), Sydney, Australia in July 2010, and has been working as a Postdoc research fellow at UNSW since. He was a visiting PhD student in the Department of Computer Science at North Carolina State University in 2008. His PhD was funded by a Fellowship from the Australian government and his research interests include Internet energy-efficiency, router buffer sizing and network design.

The conference will be conducted in English